FPGA and ASIC Implementation
IP developed by Trilinear Technologies supports implementation in both FPGA and ASIC technologies. Migrating between these two technologies requires no modification making the cores ideal for ASIC prototyping and scalable volume applications.
Language and Design
Trilinear IP cores are constructed using state of the art design techniques. Implemented in VHDL or Verilog, products are delivered to the customer in a form that can be immediately integrated into target systems, without the need for extensive modifications.
Verification is provided through two mechanisms: simulation testing and hardware validation on the Vantage platform. For Verilog designs, SystemVerilog models and test benches have been developed to ensure complete code coverage. For VHDL systems, module-level and system-level test benches have been constructed to allow for complete exercising of all code paths.
Trilinear Technologies understands that every application is different and often requires customization before a licensed IP core can be integrated into a design. All products licensed by Trilinear Technologies include customer specific modifications. Interfaces, register sets, and capabilities can all be adapted and configured to suit a customer’s specific needs.
The cores provided by Trilinear Technologies are built using the AMBA High Speed and/or AMBA Peripheral Bus interfaces, depending on the requirements of the core. Typically the AHB interface is attached to cores which require high-speed data access while the APB is usually the command and control interface. The interfaces themselves are generic and can be adapted to a wide variety of bus architectures.
IP cores provided by Trilinear Technologies come with a complete reference software driver that can be used as the basis for a production driver. The drivers are written in C and assembly language and are built using the GCC compiler chain.